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Preface
6
Acknowledgments
8
Contents
9
List of Figures
17
List of Tables
29
1 Introduction
31
1.1 Evolution of integrated circuit technology
33
1.2 Evolution of design objectives
37
1.3 The problem of power distribution
40
1.4 Deleterious effects of power distribution noise
47
1.5 Book outline
50
2 Inductive Properties of Electric Circuits
56
2.1 Definitions of inductance
57
2.2 Variation of inductance with frequency
72
2.3 Inductive behavior of circuits
81
2.4 Inductive properties of on-chip interconnect
83
2.5 Summary
87
3 Properties of On-Chip Inductive Current Loops
88
3.1 Introduction
88
3.2 Dependence of inductance on line length
89
3.3 Inductive coupling between two parallel loop segments
96
3.4 Application to circuit analysis
97
3.5 Summary
98
4 Electromigration
100
4.1 Physical mechanism of electromigration
101
4.2 Electromigration-induced mechanical stress
104
4.3 Steady state limit of electromigration damage
105
4.4 Dependence of electromigration lifetime on the line dimensions
107
4.5 Statistical distribution of electromigration lifetime
110
4.6 Electromigration lifetime under AC current
111
4.7 Electromigration in novel interconnect technologies
112
4.8 Designing for electromigration reliability
114
4.9 Summary
115
5 High Performance Power Distribution Systems
116
5.1 Physical structure of a power distribution system
117
5.2 Circuit model of a power distribution system
118
5.3 Output impedance of a power distribution system
121
5.4 A power distribution system with a decoupling capacitor
124
5.5 Hierarchical placement of decoupling capacitance
130
5.6 Resonance in power distribution networks
137
5.7 Full impedance compensation
143
5.8 Case study
145
5.9 Design considerations
148
5.10 Limitations of the one-dimensional circuit model
150
5.11 Summary
153
6 Decoupling Capacitance
154
6.1 Introduction to decoupling capacitance
155
6.2 Impedance of power distribution system with decoupling capacitors
162
6.3 Intrinsic vs intentional on-chip decoupling capacitance
174
6.4 Types of on-chip decoupling capacitors
181
6.5 On-chip switching voltage regulator
200
6.6 Summary
202
7 On-chip Power Distribution Networks
204
7.1 Styles of on-chip power distribution networks
205
7.2 Die-package interface
213
7.3 Other considerations
218
7.4 Summary
220
8 Computer-Aided Design and Analysis
221
8.1 Design flow for on-chip power distribution networks
222
8.2 Linear analysis of power distribution networks
227
8.3 Modeling power distribution networks
229
8.4 Characterizing the power current requirements of on- chip circuits
235
8.5 Numerical methods for analyzing power distribution networks
238
8.6 Allocation of on-chip decoupling capacitors
245
8.7 Summary
251
9 Inductive Properties of On-Chip Power Distribution Grids
253
9.1 Power transmission circuit
253
9.2 Simulation setup
256
9.3 Grid types
256
9.4 Inductance versus line width
261
9.5 Dependence of inductance on grid type
262
9.6 Dependence of Inductance on grid dimensions
264
9.7 Summary
269
10 Variation of Grid Inductance with Frequency
270
10.1 Analysis approach
270
10.2 Discussion of inductance variation
272
10.3 Summary
277
11 Inductance/Area/Resistance Tradeoffs
279
11.1 Inductance vs. resistance tradeoff under a constant grid area constraint
279
11.2 Inductance vs. area tradeoff under a constant grid resistance constraint
284
11.3 Summary
286
12 Scaling Trends of On- Chip Power Distribution Noise
288
12.1 Prior work
289
12.2 Interconnect characteristics
291
12.3 Model of power supply noise
297
12.4 Power supply noise scaling
299
12.5 Implications of noise scaling
306
12.6 Summary
307
13 Impedance Characteristics of Multi- Layer Grids
309
13.1 Electrical properties of multi-layer grids
311
13.2 Case study of a two layer grid
316
13.3 Design implications
325
13.4 Summary
326
14 Multiple On-Chip Power Supply Systems
328
14.1 ICs with multiple power supply voltages
329
14.2 Challenges in ICs with multiple power supply voltages
334
14.3 Optimum number and magnitude of available power supply voltages
339
14.4 Summary
344
15 On-Chip Power Distribution Grids with Multiple Supply Voltages
346
15.1 Background
348
15.2 Simulation setup
349
15.3 Power distribution grid with dual supply and dual ground
351
15.4 Interdigitated grids with DSDG
354
15.5 Paired grids with DSDG
358
15.6 Simulation results
363
15.7 Design implications
379
15.8 Summary
381
16 Decoupling Capacitors for Multi-Voltage Power Distribution Systems
383
16.1 Impedance of a power distribution system
385
16.2 Case study of the impedance of a power distribution system
393
16.3 Voltage transfer function of power distribution system
398
16.4 Case study of the voltage response of a power distribution system
403
16.5 Summary
411
17 On-chip Power Noise Reduction Techniques in High Performance ICs
412
17.1 Ground noise reduction through an additional low noise on- chip ground
414
17.2 Dependence of ground bounce reduction on system parameters
416
17.3 Summary
421
18 Effective Radii of On-Chip Decoupling Capacitors
423
18.1 Background
425
18.2 Effective radius of on-chip decoupling capacitor based on a target impedance
427
18.3 Estimation of required on-chip decoupling capacitance
429
18.4 Effective radius as determined by charge time
436
18.5 Design methodology for placing on-chip decoupling capacitors
442
18.6 Model of on-chip power distribution network
442
18.7 Case study
445
18.8 Design implications
451
18.9 Summary
452
19 Efficient Placement of Distributed On-Chip Decoupling Capacitors
454
19.1 Technology constraints
455
19.2 Placing on-chip decoupling capacitors in nanoscale ICs
456
19.3 Design of a distributed on-chip decoupling capacitor network
459
19.4 Design tradeoffs in a distributed on-chip decoupling capacitor network
464
19.5 Design methodology for a system of distributed on- chip decoupling capacitors
469
19.6 Case study
472
19.7 Summary
476
20 Impedance/Noise Issues in On- Chip Power Distribution Networks
478
20.1 Scaling effects in chip-package resonance
479
20.2 Propagation of power distribution noise
482
20.3 Local inductive behavior
484
20.4 Summary
488
21 Conclusions
490
Appendices
494
A Mutual Loop Inductance in Fully Interdigitated Power Distribution Grids with DSDG
495
B Mutual Loop Inductance in Pseudo- Interdigitated Power Distribution Grids with DSDG
497
C Mutual Loop Inductance in Fully Paired Power Distribution Grids with DSDG
499
D Mutual Loop Inductance in Pseudo-Paired Power Distribution Grids with DSDG
501
References
503
Index
526
About the Authors
530
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