Power Distribution Networks with On-Chip Decoupling Capacitors

Preface

Acknowledgments

Contents

List of Figures

List of Tables

1 Introduction

1.1 Evolution of integrated circuit technology

1.2 Evolution of design objectives

1.3 The problem of power distribution

1.4 Deleterious effects of power distribution noise

1.5 Book outline

2 Inductive Properties of Electric Circuits

2.1 Definitions of inductance

2.2 Variation of inductance with frequency

2.3 Inductive behavior of circuits

2.4 Inductive properties of on-chip interconnect

2.5 Summary

3 Properties of On-Chip Inductive Current Loops

3.1 Introduction

3.2 Dependence of inductance on line length

3.3 Inductive coupling between two parallel loop segments

3.4 Application to circuit analysis

3.5 Summary

4 Electromigration

4.1 Physical mechanism of electromigration

4.2 Electromigration-induced mechanical stress

4.3 Steady state limit of electromigration damage

4.4 Dependence of electromigration lifetime on the line dimensions

4.5 Statistical distribution of electromigration lifetime

4.6 Electromigration lifetime under AC current

4.7 Electromigration in novel interconnect technologies

4.8 Designing for electromigration reliability

4.9 Summary

5 High Performance Power Distribution Systems

5.1 Physical structure of a power distribution system

5.2 Circuit model of a power distribution system

5.3 Output impedance of a power distribution system

5.4 A power distribution system with a decoupling capacitor

5.5 Hierarchical placement of decoupling capacitance

5.6 Resonance in power distribution networks

5.7 Full impedance compensation

5.8 Case study

5.9 Design considerations

5.10 Limitations of the one-dimensional circuit model

5.11 Summary

6 Decoupling Capacitance

6.1 Introduction to decoupling capacitance

6.2 Impedance of power distribution system with decoupling capacitors

6.3 Intrinsic vs intentional on-chip decoupling capacitance

6.4 Types of on-chip decoupling capacitors

6.5 On-chip switching voltage regulator

6.6 Summary

7 On-chip Power Distribution Networks

7.1 Styles of on-chip power distribution networks

7.2 Die-package interface

7.3 Other considerations

7.4 Summary

8 Computer-Aided Design and Analysis

8.1 Design flow for on-chip power distribution networks

8.2 Linear analysis of power distribution networks

8.3 Modeling power distribution networks

8.4 Characterizing the power current requirements of on- chip circuits

8.5 Numerical methods for analyzing power distribution networks

8.6 Allocation of on-chip decoupling capacitors

8.7 Summary

9 Inductive Properties of On-Chip Power Distribution Grids

9.1 Power transmission circuit

9.2 Simulation setup

9.3 Grid types

9.4 Inductance versus line width

9.5 Dependence of inductance on grid type

9.6 Dependence of Inductance on grid dimensions

9.7 Summary

10 Variation of Grid Inductance with Frequency

10.1 Analysis approach

10.2 Discussion of inductance variation

10.3 Summary

11 Inductance/Area/Resistance Tradeoffs

11.1 Inductance vs. resistance tradeoff under a constant grid area constraint

11.2 Inductance vs. area tradeoff under a constant grid resistance constraint

11.3 Summary

12 Scaling Trends of On- Chip Power Distribution Noise

12.1 Prior work

12.2 Interconnect characteristics

12.3 Model of power supply noise

12.4 Power supply noise scaling

12.5 Implications of noise scaling

12.6 Summary

13 Impedance Characteristics of Multi- Layer Grids

13.1 Electrical properties of multi-layer grids

13.2 Case study of a two layer grid

13.3 Design implications

13.4 Summary

14 Multiple On-Chip Power Supply Systems

14.1 ICs with multiple power supply voltages

14.2 Challenges in ICs with multiple power supply voltages

14.3 Optimum number and magnitude of available power supply voltages

14.4 Summary

15 On-Chip Power Distribution Grids with Multiple Supply Voltages

15.1 Background

15.2 Simulation setup

15.3 Power distribution grid with dual supply and dual ground

15.4 Interdigitated grids with DSDG

15.5 Paired grids with DSDG

15.6 Simulation results

15.7 Design implications

15.8 Summary

16 Decoupling Capacitors for Multi-Voltage Power Distribution Systems

16.1 Impedance of a power distribution system

16.2 Case study of the impedance of a power distribution system

16.3 Voltage transfer function of power distribution system

16.4 Case study of the voltage response of a power distribution system

16.5 Summary

17 On-chip Power Noise Reduction Techniques in High Performance ICs

17.1 Ground noise reduction through an additional low noise on- chip ground

17.2 Dependence of ground bounce reduction on system parameters

17.3 Summary

18 Effective Radii of On-Chip Decoupling Capacitors

18.1 Background

18.2 Effective radius of on-chip decoupling capacitor based on a target impedance

18.3 Estimation of required on-chip decoupling capacitance

18.4 Effective radius as determined by charge time

18.5 Design methodology for placing on-chip decoupling capacitors

18.6 Model of on-chip power distribution network

18.7 Case study

18.8 Design implications

18.9 Summary

19 Efficient Placement of Distributed On-Chip Decoupling Capacitors

19.1 Technology constraints

19.2 Placing on-chip decoupling capacitors in nanoscale ICs

19.3 Design of a distributed on-chip decoupling capacitor network

19.4 Design tradeoffs in a distributed on-chip decoupling capacitor network

19.5 Design methodology for a system of distributed on- chip decoupling capacitors

19.6 Case study

19.7 Summary

20 Impedance/Noise Issues in On- Chip Power Distribution Networks

20.1 Scaling effects in chip-package resonance

20.2 Propagation of power distribution noise

20.3 Local inductive behavior

20.4 Summary

21 Conclusions

Appendices

A Mutual Loop Inductance in Fully Interdigitated Power Distribution Grids with DSDG

B Mutual Loop Inductance in Pseudo- Interdigitated Power Distribution Grids with DSDG

C Mutual Loop Inductance in Fully Paired Power Distribution Grids with DSDG

D Mutual Loop Inductance in Pseudo-Paired Power Distribution Grids with DSDG

References

Index

About the Authors